Anna University Questions - CS182 - CS9152 Digital Principles and System Design April May 2014, Computer Science and Engineering (CSE), Second Semester, Regulation 2004/2008

Exam |
B.E/B.Tech. (Full
Time) DEGREE END SEMESTER EXAMINATIONS |

Academic
Year |
April May 2014 |

Subject
Code |
CS182 / CS9152 |

Subject
Name |
Digital Principles and System Design |

Branch |
Computer Science and Engineering |

Semester |
Second Semester |

Regulation |
2004/2008 |

**B.E / B.Tech. (Full Time) DEGREE END SEMESTER EXAMINATIONS, APRIL / MAY 2014**

Computer Science
and Engineering

Second Semester

**CS182 / CS9152**

**DIGITAL PRINCIPLES AND SYSTEM DESIGN**

(Regulation 2004/2008)

Time : 3 Hours Answer A L L Questions Max. Marks 100

**PART-A (10 x 2 = 20 Marks)**

1. State distributive law and
associative law.

2. Obtain 2's complement of 01110110

3. Draw the full adder circuit using
two half adders.

4. Draw the logic diagram of carry
look ahead generator

5. What is a decoder?

6. Draw the diagram of three state
buffer.

7. Draw the characteristic table of JK
and T flip flops.

8. Draw the logic diagram of SR latch.

9. What is a fundamental mode of
operation?

10. Draw the excitation table of SR
latch using NAND gates.

**Part-B (5* 16 = 80 Marks)**

11. Minimize F(A,B,C,D) = ∑(0,5,7,8,9,10,11,14,15)
using QM method (16)

12. a) Convert the following into
other canonical forms (16)

F(x,y,z) = ∑(0,2,3,5,7,9,11,15)

F(A,B,C,D) = π(3,4,6,7,8,9,1
1,12,13)

**OR**

b) Explain how the binary code is converted
to gray code. (16)

13. a) i) Explain Priority encoder (8)

ii) Write the HDL gate level
description of the above circuit (8)

**OR**

b) i) Draw the 4 bit magnitude
comparator and explain. (8)

ii) Draw block diagram of BCD adder
and explain. (8)

14. a) Design a mod 6 synchronous
counters using JK flip flops. (16)

**OR**

b) i) Draw the diagram of universal
shift register (6)

ii) Draw the diagram of 4 bit binary
counter with parallel load and explain (10)

15. a) An asynchronous sequential
circuit is described by the excitation function Y=X

_{1}X_{2}'+(x_{1}+x_{2}')y and the output function z=y. (16)
i) Draw the logic diagram of the
circuit

ii) Derive the transition table and
output map

iii) Obtain a two-state flow table

iv) Describe in words the behavior of
the circuit

**OR**

b) i) Explain race free assignment
with appropriate example. (8)

ii) Explain static 0 and static 1
hazard in combinational circuits. (8)

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