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## Anna University CS 273 / CS9204 – COMPUTER ARCHITECTURE April May 2014, Computer Science Engineering, Third Semester, Regulations 2004/2008

 Exam B.E/B.Tech. (Full Time) DEGREE END SEMESTER EXAMINATIONS Academic Year April May 2014 Subject Code CS 273 / CS 9204 Subject Name Computer Architecture Branch Computer Science and Engineering Semester Third Semester Regulation 2004 and 2008

B.E / B.Tech. (Full Time) DEGREE END SEMESTER EXAMINATIONS, APRIL / MAY 2014
Computer Science and Engineering
Third Semester
CS 273 / CS9204 – COMPUTER ARCHITECTURE
(Regulations 2004/2008)
Time : 3 Hours                      Answer A L L Questions                Max. Marks 100
PART-A (10 x 2 = 20 Marks)

1. State the CPU performance equation
2. Differentiate RISC Vs CISC
3. Distinguish between horizontal and vertical microprogramming
4. Define Nano programming
5. What is the need for Speculation?
6. What is Microroutine?
7. What is meant by interleaved memory?
8. What is the purpose of Dirty/Modified bit in Cache memory?
9. Differentiate Programmed I/O and Interrupt I/O
10. What is Parallel Port?

Part-B (5* 16 = 80 Marks)
11. (i) Multiply the following pair of signed nos. using Booth's bit-pair recoding of the multiplier. A = -8 (Multiplicand) and B = -8 (Multiplier) (6)
(ii) Explain the following addressing modes with an example and suggest a use for those addressing modes: (10)
i. Register Indirect
ii. Auto increment

12. (a) Assume the single bus organization and write down the control sequence for the instruction, SUB (R1), (R2)+, R3 assuming a three address dst., src1 , src2 format (16)
(OR)
12. (b) Explain the Hardwired and Micro programmed Control systems (16)

13. (a) (i) Explain Pipelining and Hazards. List down and brief about the types of hazards with examples (10)
(ii) Explain about various Branch Prediction Techniques (6)
(OR)
13. (b) Explain Dynamic scheduling with Tomosulos algorithm with an example (16)

14. (a) (i) Discuss the following terms w.r.t. virtual memory:                          (10)
TLB, Page Map Table, Least recently used, Page Table Base Register, Virtual address
(ii) Write short notes on Cache memory (6)
(OR)
14. (b) Write short notes on the following:
(i) Secondary storage devices (8)
(ii) Associative memory (8)

15. (a) Explain in detail about the Bus Arbitration techniques in DMA (16)
(OR)
15.(b) (i) Explain in detail about any two Standard Input and Output Interfaces required to connect the I/O device to the Bus. (8)
(ii) Draw different memory address layouts and brief about the technique used to increase the average rate of fetching words from the main memory (8)

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